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32-bit single- axis/dual-axis quadrature counter features: ? direct interface with incremental encoders ? read/write registers for count and i/o modes. count modes include: non-quadrature (up/down), quadrature (x1, x2, x4.) free-run, non-recycle, modulo-n and range limit ? programmable ios for index and marker flags ? separate mode-control registers for each axis ? 40mhz count frequency at 5v; 20mhz count frequency at 3v ? sets of 32-bit counters, input registers, output registers, comparators and octal status registers for each axis ? digital filtering of the input quadrature clocks for noise immumity. ? pin selectable 3-state hex / octal bus ? 3v to 5.5v operating voltage range ? available in four different configurations identified by the following suffixes: dh = dual-axis with pin selectable hex/octal io bus do = dual-axis octal io bus sh = single-axis pin selectable hex/octal io bus so = single axis octal io bus LS7766dh-ts; LS7766do, LS7766do-s, LS7766do-ts; LS7766so, LS7766so-s, LS7766so-ts; LS7766sh-ts p/ n = dip ; p/n -s = soic ; p /n- ts = tssop general description: the LS7766 consists of two identical modules of 32-bit programmable up/down counters (cntr) with direct interface to incremental encod- ers. the modules can be configured to operate as quadrature-clock counters or non-quadrature up/down counters. in both quadrature and non-quadrature modes, the modules can be further configured into free-running, non-recycle, modulo-n and range-limit count modes. the mode configuration is made via two octal read/write addressable mode control registers, mcr0 and mcr1. data can be written into a 32-bit input data register (idr), organized in addressable word seg- ments using the hex io bus or in byte segments using the octal io bus. the idr can be used to store target encoder positions and com- pared with the cntr for generating marker flags when the cntr reaches the target value. a 32-bit digital comparator is included for monitoring the equality of the cntr to the idr. snapshots of the cntr value can be stored in a read-addressable 32-bit output data register (odr). the odr can be read in word segments or byte seg- ments in accordance with the selected bus width. data transfers among the registers and various register reset functions are per- formed by means of a write-addressable octal transfer control register (tcr). a read-addressable octal status register (str), stores the count related status information such as cntr overflow, underflow, count direction, etc. october 2007 7766-102307-1 lsi/csi l si c o m p u t e r sy s t e m s , i n c . 1 2 3 5 w a l t w h i t m a n r o a d , m e l v i l l e , n y 1 1 7 4 7 ( 6 3 1 ) 2 7 1 - 0 4 0 0 f a x ( 6 3 1 ) 2 7 1 - 0 4 0 5 LS7766 pin assignment - top view u l a3800 1 48 lsi LS7766dh 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 rs2 rs1 rs0 nc db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 nc nc nc v ss v dd pcko pcki rd/ wr/ cs/ nc x1b x0flga x1flga x1cko io16/ x0/_x1 x0cko x0flgb nc x0indx/ x0a x0b nc x1a x1indx/ x1flgb v ss
pin assignment - top view pin assignment - top view pin assignment - top view 7766 - 110806 -2 1 38 lsi LS7766sh 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 rs2 rs1 rs0 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 v dd pcko pcki rd/ nc wr/ cs/ nc b io16/ v ss cko flgb flga indx/ a nc nc nc db15 1 24 lsi LS7766so 2 3 4 5 6 7 8 10 11 12 23 22 21 20 19 18 17 16 15 14 13 rs2 rs1 rs0 db0 db1 db2 db3 db4 db5 db6 db7 v ss v dd pcko pcki rd/ wr/ cs/ cko b flgb flga indx/ a 9 1 28 lsi LS7766do 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 x1a x1b cs/ wr/ rd/ pcki v dd rs2 rs1 rs0 db0 db1 db2 db3 x1indx/ x1flga x1flgb x0/_x1 x0flgb x0flga x0indx/ x0a db7 db5 db4 x0b v ss db6
register description: following is a list of the hardware registers for the single-axis device. for the dual axis device, these registers are duplicated for the second axis. idr the idr is a 32-bit data register directly address- able for write. in the octal bus-configuration, the input data is written in byte segments of byte0 (idr0), byte1 (idr1), byte2 (idr2) and byte3 (idr3). in the hex bus- configuration the data is written in word segments of word0 (idr1:idr0) and word1 (idr3:idr20). b31------------------------------------------------------------------- b0 idr: idr3 idr2 idr1 idr0 b7------------b0 b7-----------b0 b7-----------b0 b7---------b0 ----- byte3------ -----byte2----- -----byte1----- -----byte0----- --------------- word1---------------- --------------- word0 ------------ the idr serves as the input portal for the counter (cntr) since the cntr is not directly addressable for either read or write. in order to preset the cntr to any desired value the data is first written into the idr and then transferred to the cntr. in mod-n and range-limit count modes the idr serves as the repository for the division factor n and the count range-limit, respectively. the idr can also be used to hold a target position data for comparing with the running cntr. a compare equality flag is generated at idr = cntr to signal the event of arriving at the target. cntr: the cntr is a 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at a and b inputs or alternatively, in non- quadrature mode, pulses applied at the a input. the cntr is not directly accessible for read or write; instead it can be preloaded with data from the idr or it can port its own data out to the odr which in turn can be ac- cessed by read operation. in both quadrature and non- quadrature modes, the cntr can be further configured into either free-running or single-cycle or mod-n or range-limit mode. in quadrature mode, the count resolution is programmable to be x1 or x2 or x4 of the a quad b cycles. odr: the odr is a 32-bit data register directly addressable for read. in the octal bus-configuration, the output data is read in byte segments of byte0 (odr0), byte1 (odr1), byte2 (odr2), and byte3 (odr3). in the hex bus- configuration the data is read in word segments of word0 (odr1:odr0) and word1 (odr3:odr2). b31------------------------------------------------------------------- b0 odr: odr3 odr2 odr1 odr0 b7------------b0 b7-----------b0 b7-----------b0 b7---------b0 ----- byte3------ -----byte2----- -----byte1----- -----byte0----- --------------- word1---------------- --------------- word0 ------------ str: the str is an 8-bit status register indicating count related status. str: cy bw cmp idx cen 0 u/d s b7 b6 b5 b4 b3 b2 b1 b0 an individual str bit is set to 1 when the bit related event has taken place. the str is cleared to 0 at power-up. the str can also be cleared through the control register tcr with the exception of bit_1(u/d) and bit3_(cen). these two str bits always indicate the instantaneous status of the count_direction and count_enable assertion/de-assertion. the str bits are described below: b7 (cy): carry; set by cntr overflow b6 (bw): borrow; set by cntr underflow b5 (cmp): set when cntr = pr b4 (idx): set when indx input is at active level b3 (cen): set when counting is enabled, reset when counting is disabled b2 (0): always 0 b1 (u/d): set when counting up, reset when counting down b0 (s): sign of count value; set when negative, reset when positive 7766-042407-3 tcr: the tcr is a write only register, which when written into, gener- ates transient signals to perform load and reset operations as described below: tcr: b7 b6 b5 b4 b3 b2 b1 b0 b0 = 0: nop = 1: reset cntr to 0. (should not be combined with load_cntr operation). b1 = 0: nop = 1: load cntr from idr. affects all 32 bits. (should not be combined with reset_cntr operation) b2 = 0: nop = 1: load odr from cntr. affects all 32 bits. b3 = 0: nop = 1: reset str. affects status bits for carry, borrow, compare and index. status bits corresponding to count_enable, count direction and sign are not affected b4 = 0: nop. 1: master reset. resets mcr0, mcr1, idr, odr, str b5 = 0: nop 1: set sign bit (str bit0) b6 = 0: nop 1: reset sign bit (str bit0) b7 = x: not used.
mcr0 : the mcr0 is an 8-bit read/write register which configures the counting modes and the index input functionality. upon power-up, the mcr0 is cleared to zero. mcr0: b7 b6 b5 b4 b3 b2 b1 b0 b1b0 = 00: non-quadrature count mode (a = clock, b = direction). = 01: x1 quadrature count mode (one count per quadrature cycle). = 10: x2 quadrature count mode (two counts per quadrature cycle). = 11: x4 quadrature count mode (four counts per quadrature cycle). b3b2 = 00: free-running count mode. = 01: single-cycle count mode (cntr disabled with carry and borrow , re-enabled with reset or load ) = 10: range-limit count mode (up and down count ranges are limited between idr and zero, respectively. counting freezes at these limits but resumes when the direction is reversed) = 11: modulo-n count mode (input count clock frequency is divided by a factor of [n+1], where n = idr. in up direction, the cntr is cleared to 0 at cntr = idr and up count continues. in down direction, the cntr is preset to the value of idr at cntr = 0 and down count continues. a mod-n rollover marker pulse is generated at each limit at the flga output). b5b4 = 00: disable indx/ input. = 01: configure indx/ input as the load_cntr input (transfers idr to cntr). = 10: configure indx/ as the reset _cntr input (clears cntr to 0). = 11: configure indx/ as the load_odr input (transfers cntr to odr). b6 = 0: asynchronous index. = 1: synchronous index (overridden in non-quadrature mode). b7 = 0: input filter clock (pck) division factor = 1. filter clock frequency = f pck . = 1: input filter clock division factor = 2. filter clock frequency = f pck /2. mcr1 : the mcr1 is an 8-bit read/write register which configures the flga and flgb output functionality. in addition, the mcr1 can be used to enable/disable counting.upon power-up, the mcr1 is cleared to zero: mcr1: b7 b6 b5 b4 b3 b2 b1 b0 b0 = 1: enable carry on flga (flags cntr overflow; latched or unlatched logic low on carry). b1 = 1: enable borrow on flga (flags cntr underflow, latched or unlatched logic low on borrow). b2 = 1: enable compare on flga (in free-running count mode a latched or unlatched logic low is generated in both up and down count directions at cntr = idr. in contrast, in range-limit and mod-n count modes a latched or unlatched low is generated at cntr = idr in the up-count direction only. b3 = 1: enable index on flga (flags index, latched or unlatched logic low when indx input is at active level) b5b4 = 00: flgb disabled (fixed high) = 01: flgb = sign , high for negative signifying cntr underflow, low for positive. = 10: flgb = up/down count direction, high in count-up, low in count-down. b6 = 0: enable counting. = 1: disable counting. b7 = 0: flga is latched. = 1: flga is non-latched and instantaneous. note : carry, borrow, compare and index can all be simultaneously enabled on flga. 7766-111406-4
table 1 databus selected register cs/ rs2 rs1 rs0 rd/ wr/ register map operation 1 x x x x x none none none 0 0 0 0 0 1 mcr0 dbl read 0 0 0 1 0 1 mcr1 dbl read 0 0 1 0 0 1 odr0 dbl read 0 0 1 1 0 1 odr1 dbl read 0 1 0 0 0 1 odr2 dbl read 0 1 0 1 0 1 odr3 dbl read 0 1 1 0 0 1 str dbl read 0 0 0 0 1 0 mcr0 dbl write 0 0 0 1 1 0 mcr1 dbl write 0 0 1 0 1 0 idr0 dbl write 0 0 1 1 1 0 idr1 dbl write 0 1 0 0 1 0 idr2 dbl write 0 1 0 1 1 0 idr3 dbl write 0 1 1 0 1 0 tcr dbl write table 2 databus selected register cs/ rs2 rs1 rs0 rd/ wr/ register map operation 1 x x x x x none none none 0 0 0 0 0 1 [mcr1:mcr0] [dbh:dbl] read 0 0 1 0 0 1 [odr1:odr0] [dbh:dbl] read 0 1 0 0 0 1 [odr3:odr2] [dbh:dbl] read 0 1 1 0 0 1 [str] [dbl] read 0 0 0 0 1 0 [mcr1:mcr0] [dbh:dbl] write 0 0 1 0 1 0 [idr1:idr0] [dbh:dbl] write 0 1 0 0 1 0 [idr3:idr2] [dbh:dbl] write 0 1 1 0 1 0 [tcr] [dbl] write note 1 . x indicates don? care case. note 2 . dbl stands for db <7:0> ; dbh stands for db <15:8>. 7766-111406-5 i/o pins : the following is a description of the input/out pins. rs0, rs1, rs2 inputs. these three inputs select the hardware registers for read/write access according to table 1 and table 2. table 1 applies to octal bus configuration. table 2 applies to hex bus configuration.
x0/_x1 input. the x0/_x1 input selects between axis-0 and axis-1 for read and write operations. a low at this input selects axis-0 while a high selects axis-1. rd/ input. a low on rd/ input accesses an addressed register(s) for read and places the data on the databus, db<15:0> in accordance with table 1 and table 2. cs/ input. a low on the cs/ input enables the chip for read or write operation. when the cs/ input is high, read and write operations are disabled and the databus, db<15:0> is placed in a high impedance state. wr/ input. a low pulse on the wr/ input writes the data on the databus, db<15:0> into the addressed register according to table 1 and table 2. the write operation is completed at the trailing edge of the wr/ pulse. pcki, pcko . input, output. a clock applied at pcki in- put is used for validating the logic states of the a and b quadrature clocks and the indx/ input. alternatively, a crystal oscillator connected between pcki and pcko can be used to generate the filter clock. the pck input frequency, f pck is divided down by a fac- tor of 1 or 2 according to bit7 of mcr0. the resultant clock is used to sample the logic levels of the a, the b and the indx inputs. if a logic level at any of these inputs remains stable for a minimum of two filter clock periods, it is validated as a correct logic state. the pcki input is common to both axes, but the filter clock frequency for any axis is set by its associated mcr0 register. in non-quadrature mode, no filter clock is used and the pcki input should be connected to either v dd or gnd. x0a, x0b inputs. these are the a and b count inputs in axis-0. these inputs can be configured to function either in quadrature mode or in non-quadrature mode. the con- figuration is made through mcr0. in quadrature mode, a and b clocks are 90 degrees out of phase such as the output from an incremental encoder. when a leads b in phase, the cntr counts up and when b leads a in phase, the cntr counts down. in non-quadrature mode, a serves as the count input while b controls the count direction. when b is high , positive transitions at the a input causes the cntr to count up . conversely, when b is low , the positive transi- tion at the a input causes the cntr to count down . in quadrature mode, a and b inputs are sampled by an internal filter clock generated from the pcki input. in non-quadrature mode, a and b inputs are not sampled and the count clocks are applied to the cntr, bypassing the filter circuit. x1a , x1b : these are the a and b inputs corresponding to axis-1, . functionally, they are identical with the a and b inputs of axis-0. x0indx/ input. the indx/ input in axis-0. the indx/ in- put can be configured to function as load_cntr or re- set_cntr or load_odr input via mcr0. in quadrature mode the indx/ input can be configured to operate in either synchronous or asynchronous mode. in the syn- chronous mode the indx/ input is sampled with the same filter clock used for sampling the a and the b in- puts and must satisfy the phase relationship with a and b in which indx/ is at the active level during a mini- mum of a quarter cycle of both a and b high or both a and b low. the active level of the indx/ input is logic low. in non-quadrature mode the indx/ input is un- conditionally set to the asynchronous mode. in the asynchronous mode the indx/ input is not sampled and can be applied in any phase relationship with re- spect to the a and b inputs. the indx/ input can be either enabled or disabled in both quadrature and non-quadrature modes. x1indx/. the indx/ input corresponding to axes-1. functionally, it is identical with the indx/ input of axis-0. io16/ input. when low, hex databus configuration is in- voked in accordance with table 2. when high, octal da- tabus configuration is invoked in accordance with ta- ble 1. this input has an internal pull-up. x0flga output. the flga output in axis-0. the flga output is configured by mcr1 register to function as carry and/or borrow and/or compare and/or index flag. a carry flag is generated when the cntr overflows, a borrow flag is generated when the cntr underflows, a compare flag is generated by the condition, cntr = idr and index flag is generated when index input is at active level. the flga output can be configured to pro- duce outputs in either latched mode or instantaneous mode. in the latched mode when the selected event of carry or borrow or compare or index has taken place, flga switches low and remains low until the status reg- ister, str is cleared. in the instantaneous mode, a neg- ative pulse is generated instantaneously when the event takes place. the flga output can be disabled to remain at a fixed logic high. x1flga output. the flga output corresponding to axes-1. functionally, it is identical with the flga output of axis-0. 7766-110806-6
x0flgb output. the flgb output in axis-0. the flgb output is configured by mcr1 to function as either sign or up/down count direction indicator. when configured as sign, the flgb output remains high when cntr is in an underflow state (caused by down counts at or below zero), indicating a negative number. when the cntr counts up past zero, flgb switches low, indicating a positive number. when configured as up/down indicatior, a high at the flgb indicates that the current count direction is up (in- cremental) whereas a low indicates that the direction is down or decremental. the flgb output can be disabled to remain at a fixed logic high. 7766-062207-7 x1flgb output . the flgb output of axis-1. functionally, it is identical with the flgb output of axis-0. x0cko output . axis-0 count clock output. in non- quadrature mode, the cko output is identical with the in- put-a clock. in quadrature mode, cko is derived from the filtered and decoded quadrature clocks applied at the a and b inputs. in either mode cko is a true representative of the internal count clock. x1cko output . axis-1 count clock output. functionally, it is identical with the cko output of axis-0. v dd . supply voltage. positive terminal. gnd . supply voltage. negative terminal. the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
absolute maximum ratings: parameter symbol values unit voltage at any input v in v ss - 0.3 to v dd + 0.3 v supply voltage v dd +7.0 v operating temperature t a -25 to +80 o c storage temperature t stg -65 to +150 o c dc electrical characteristics . (t a = -25 o c to +80 o c, v dd = 3v to 5.5v) parameter symbol min. value max.value unit remarks supply voltage v dd 3.0 5.5 v - supply current i dd - 800 ? all clocks off input logic low v il - 0.15v dd v - input logic high v ih 0.5v dd - v - input leakage current i ilk - 30 na - data bus leakage current i dlk - 60 na data bus off data bus source current i dbh 2.0 - ma v o = v dd - 0.5v, v dd = 5v data bus sink current i dbl -6.0 - ma v o = 0.5v, v dd = 5v flga, flgb, int/ source i osrc 1.0 - ma v o = v dd - 0.5v, v dd = 5v flga, flgb, int/ sink i osnk -6.0 - ma v o = 0.5v, v dd = 5v transient characteristics . (t a = -25 o to +80 o c, v dd = 3v to 5.5v) parameter symbol min. value max.value unit remarks read cycle (see fig. 2) rd/ pulse width t r1 80 - ns - cs/ set-up time t r2 80 - ns - cs/ hold time t r3 0 - ns - rs<2:0> set-up time t r4 80 - ns - rs<2:0> hold time t r5 10 - ns - x0/_x1 set-up time t r6 80 - ns - x0/_x1 hold time t r7 10 - ns - db<15:0> accesstime t r8 80 - ns access starts when both rd/ and cs/ are low. db<15:0> release time t r9 - 35 ns release starts when either rd/ or cs/ is terminated. back to back read delay t r10 10 - ns - write cycle (see fig. 3) wr/ pulse width t w1 45 - ns - cs/ set-up time t w2 45 - ns - cs/ hold time t w3 0 - ns - rs<2:0> set-up time t w4 45 - ns - rs<2:0> hold time t w5 10 - ns - x0/_x1 set-up time t w6 45 - ns - x0/_x1 hold time t w7 10 - ns - db<15:0> set-up time t w8 45 - ns - db<15:0> hold time t w9 10 - ns - back to back write delay t w10 90 - ns - 7766-110806-8
for v dd = 3.3v ?0% parameter symbol min. value max.value unit remarks quadrature mode (see fig. 4 - 6) pcki high pulse width t 1 24 - ns - pcki low pulse width t 2 24 - ns - pcki frequency f pck - 20 mhz - filter clock (ff) period t 3 50 - ns t 3 = t 1 + t 2 , mdr0 <7> = 0 t 3 100 - ns t 3 = t 1 + t 2 , mdr0 <7> = 1 filter clock frequency f f - 20 mhz f f = 1/t 3 quadrature separation t 4 52 - ns t 4 > t 3 quadrature clock pulse width t 5 105 - ns t 5 > 2t 3 quadrature clock frequency f qa , f qb - 4.5 mhz f qa = f qb < 1/4t 3 quadrature clock to count delay t q1 4t 3 5t 3 - - x1, x2, x4 count clock pulse width t q2 25 - ns t q2 = t 3 /2 quadrature clock to flga delay t fda 4.5t 3 5.5t 3 ns - quadrature clock to flgb delay t fdb 3t 3 4t 3 ns - indx/ input pulse width t id 60 - ns t id > t 4 indx/ set-up time t is 10 - ns - indx/ hold time t ih 10 - ns - flga output width t fw 50 - ns t fw ? t 4 non-quadrature mode (see fig. 7 - 8) clock a - high pulse width t 6 24 - ns - clock a - low pulse width t 7 24 - ns - direction input b set-up time t 8s 24 - ns - direction input b hold time t 8 20 - ns - clock frequency f a - 20 mhz f a = (1/(t 6 + t 7 )) clock to flga out delay t 9 - 40 ns - flga out pulse width t 10 24 - ns t 10 = t 7 indx/ pulse width t 11 30 - ns - 7766-110806-9 for v dd = 5v ?0% parameter symbol min. value max.value unit remarks quadrature mode (see fig. 4 - 6) pck high pulse width t 1 12 - ns - pck low pulse width t 2 12 - ns - pck frequency f pck - 40 mhz - filter clock (ff) period t 3 25 - ns t 3 = t 1 + t 2 , mdr0 <7> = 0 t 3 50 - ns t 3 = t 1 + t 2 , mdr0 <7> = 1 filter clock frequency f f - 40 mhz - quadrature separation t 4 26 - ns t 4 > t 3 quadrature clock pulse width t 5 52 - ns t 5 > 2t 3 quadrature clock frequency f qa , f qb - 9.6 mhz f qa = f qb < 1/4t 3 quadrature clock to count delay t q1 4t 3 5t 3 - - x1, x2, x4 count clock pulse width t q2 12 - ns t q2 = t 3 /2 quadrature clock to flga delay t fda 4.5t 3 5.5t 3 ns - quadrature clock to flgb delay t fdb 3t 3 4t 3 ns - indx/ input pulse width t id 32 - ns t id > t 4 indx/ set-up time t is 5 - ns - indx/ hold time t ih 5 - ns - flga output width t fw 24 - ns t fw ? t 4 non-quadrature mode (see fig. 7 - 8) clock a - high pulse width t 6 12 - ns - clock a - low pulse width t 7 12 - ns - direction input b set-up time t 8 12 - ns - direction input b hold time t 8 10 - ns - clock frequency f a - 40 mhz f a = (1/(t 6 + t 7 )) clock to flga out delay t 9 - 20 ns - flga out pulse width t 10 12 - ns t 10 = t 7 indx/ pulse width t 11 15 - ns -
note 1 . synchronous mode index coincident with both a and b high. note 2. synchronous mode index coincident with both a and b low. note 3. f f is the internal effective filter clock. figure 4. pcki, a, b and indx/ 7766-110806-10 rd/ cs/ rs x0/_x1 db valid data valid data tr 1 tr 10 tr 2 tr 3 tr 4 tr 5 tr 6 tr 7 tr 8 tr 9 figure 2. read cycle tw 5 tw 7 tw 9 tw 3 tw 2 tw 4 tw 6 tw 8 input data tw 1 tw 10 input data wr/ cs/ rs x0/_x1 db figure 3. write cycle pcki t 1 t 2 f f (note 3) (mcr0 <7> = 0) f f (note 3) (mcr0 <7> = 1) a b indx/ t 3 t 3 t 5 t 5 t 4 t 4 t 4 t 4 note 1 note 2 t id t is t ih t is t ih
figure 5. a/b quadrature clocks vs output clock, cko note . cko is identical with internal count clock. note . flga is in non-latched mode. figure 6. quadrature clocks vs flga, flgb outputs 7766-042407-11 up down a b cko t fda cntr flga flgb (up/dn) flgb (sign) t fw t fdb positive negative cy cmp bw fffffc fffffd fffffe ffffff ffffff fffffe fffffd 000000 000001 000002 000001 000000 (shown with pr=000oo1) (x4 mode) up down a b cko cko cko (x4 mode) (x2 mode) (x1 mode) t q1 t q2
figure 7. count (a) and direction (b) inputs in non-quadrature mode figure 8. single-cycle, non-quadrature figure 9. modulo-n, non-quadrature figure 10. range-limit, non-quadrature 7766-110806-12 down up down t 6 t 7 t 8s t 8h b a flga cntr a b 0 2 1 0 cmp (shown with pr = 3) bw up down 1 2 3 3 0 1 2 1 0 flga cntr a b 000003 000002 000001 cmp (shown with pr = 3) up down 000000 000001 000002 000000 bw bw bw cmp cmp cmp indx flga cntr a b ffffffc ffffffd ffffffe fffffff 0 2 1 0 fffffff cy t 9 t 10 t 11 cntr disabled cntr disabled (shown with pr= 2) cntr enabled (load cntr)
7766-110806-13 figure 11. LS7766 block diagram for single-axis str (8) mux buffer and/or/buf mcr1(8) mcr0(8) idr3(8) idr2(8) idr1(8) idr0(8) c o m p cntr (32) mode logic count clock & index generator osc read/write & axis select logic register select logic input buffer output 3-state buffer marker logic odr3(8) odr2(8) odr1(8) odr0(8) read write read read clock read cy, bw, cmp, indx, sign, up/down out-bus<15:0> ck0 flga flgb flag-masks write read in-bus<15:0> out-bus<15:0> modes, flag-masks clock indx cmp cy, bw, sign out-bus<15:0> in-bus<15:0> a b indx/ pcki pck0 rd/ wr/ cs/ x0/_x1 rs<2:0> io16/ db<15:0> write tcr(8) ld/set/reset
7766-111406-14 a<4> a<3> a<2> a<1> wr/ rd/ rs2 rs1 rs0 x0/_x1 cs/ address decode pc isa / eisa bus iow/ ior/ d<15:0 > a< 4:1 > a< 7:5> LS7766 aen figure 12. LS7766 to isa / eisa interface with hex bus db<15:0> io16/ d<7> d<6> d<5> d<4> d<3> d<2> d<1> d<0> a2 a1 a0 a3 wr/ rd/ db7 db6 db5 db4 db3 db2 db1 db0 rs2 rs1 rs0 x0/_x1 cs/ address decode mc68hc000 d<7: 0> a 3 - a 0 a<23: 20> LS7766 figure 13. LS7766 to mc68hc000 interface with octal bus a<23:a 0 > d<7: 0> r/w lds dtack/ 15pf 15pf 40mhz 1 m w pcki pcko

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